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Risc V Single Cycle Stub
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秦槿
Risc V Single Cycle Stub
Commits
7c2b4cc5
Commit
7c2b4cc5
authored
2 years ago
by
秦槿
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sltu
parent
e894eb1a
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1 changed file
xgriscv_datapath.v
+6
-3
6 additions, 3 deletions
xgriscv_datapath.v
with
6 additions
and
3 deletions
xgriscv_datapath.v
+
6
−
3
View file @
7c2b4cc5
...
...
@@ -52,12 +52,13 @@ module datapath(
//更新pc
wire
[
`ADDR_SIZE
-
1
:
0
]
base
,
offset
;
wire
stall
=
1'b0
;
wire
[
`ADDR_SIZE
-
1
:
0
]
newpc
;
pcenr
pcr
(
clk
,
reset
,
~
stall
,
newpc
,
pc
);
addr_adder
pcadder
(
pc
,
`ADDR_SIZE
'b100
,
pcplus4
);
sl1
pcsft
(
immout
,
immoutsft
);
addr_adder
pcjal
(
pc
,
immoutsf
t
,
pcbranch
);
sl1
pcsft
(
immout
,
shftimm
);
addr_adder
pcjal
(
base
,
offse
t
,
pcbranch
);
wire
[
4
:
0
]
shamt
;
...
...
@@ -68,7 +69,9 @@ module datapath(
mux3
#(
32
)
mx2
(
rdata1
,
0
,
pc
,
alusrca
,
a
);
//alu input a
mux2
#(
5
)
mx3
(
rdata2
[
4
:
0
],
instr
[
24
:
20
],
itype
,
shamt
);
//alu input shamt
mux2
#(
32
)
mx4
(
pcplus4
,
pcbranch
,
pcsrc
,
newpc
);
//pc input
mux2
#(
32
)
mx5
(
wdata
,
pcplus4
,
jal
,
wdata
);
// wdata input pcplus4
mux2
#(
32
)
mx5
(
shftimm
,
immout
,
jalr
,
offset
);
//sum input b
mux2
#(
32
)
mx6
(
pc
,
rdata1
,
jalr
,
base
);
//sum input a
mux2
#(
32
)
mx7
(
wdata
,
pcplus4
,
jal
,
wdata
);
//wdata input pcplus4
imm
im
(
iimm
,
simm
,
bimm
,
uimm
,
jimm
,
immctrl
,
immout
);
...
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