From 7c2b4cc5f0648656e7b9af1d17d3ef7263b5f163 Mon Sep 17 00:00:00 2001 From: Qin Jin <137202313@qq.com> Date: Sun, 5 Feb 2023 12:24:37 +0800 Subject: [PATCH] sltu --- xgriscv_datapath.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/xgriscv_datapath.v b/xgriscv_datapath.v index 6ea1581..a341017 100644 --- a/xgriscv_datapath.v +++ b/xgriscv_datapath.v @@ -52,12 +52,13 @@ module datapath( //更新pc + wire [`ADDR_SIZE-1:0] base, offset; wire stall = 1'b0; wire [`ADDR_SIZE-1:0] newpc; pcenr pcr(clk, reset, ~stall, newpc, pc); addr_adder pcadder(pc, `ADDR_SIZE'b100, pcplus4); - sl1 pcsft(immout, immoutsft); - addr_adder pcjal(pc, immoutsft, pcbranch); + sl1 pcsft(immout, shftimm); + addr_adder pcjal(base, offset, pcbranch); wire [4:0] shamt; @@ -68,7 +69,9 @@ module datapath( mux3 #(32) mx2(rdata1, 0, pc, alusrca, a); //alu input a mux2 #(5) mx3(rdata2[4:0], instr[24:20], itype, shamt); //alu input shamt mux2 #(32) mx4(pcplus4, pcbranch, pcsrc, newpc);//pc input - mux2 #(32) mx5(wdata, pcplus4, jal, wdata);// wdata input pcplus4 + mux2 #(32) mx5(shftimm, immout, jalr, offset);//sum input b + mux2 #(32) mx6(pc, rdata1, jalr, base);//sum input a + mux2 #(32) mx7(wdata, pcplus4, jal, wdata);//wdata input pcplus4 imm im(iimm, simm, bimm, uimm, jimm, immctrl, immout); -- GitLab