diff --git a/xgriscv_alu.v b/xgriscv_alu.v
index 2d73c34ee9bc061441c1e3a8e7ed777bc7222a91..c96f76d08e0b391ac86e73f31c74f331555aebf0 100644
--- a/xgriscv_alu.v
+++ b/xgriscv_alu.v
@@ -34,6 +34,8 @@ module alu(
 
 		`ALU_CTRL_XOR:      aluout <= a ^ b;
 		`ALU_CTRL_AND:      aluout <= a & b;
+
+		`ALU_CTRL_SLL:      aluout <= a << shamt;
 		//`ALU_CTRL_ZERO		
 		default: 			aluout <= `XLEN'b0; 
 	    endcase
diff --git a/xgriscv_controller.v b/xgriscv_controller.v
index 00bca81e21b1fab024068eb2f33797e67afcc254..2eab5fb09b2d93c84b73a9db4f5513727596742a 100644
--- a/xgriscv_controller.v
+++ b/xgriscv_controller.v
@@ -111,7 +111,11 @@ module controller(
                     `FUNCT3_ADDI:	aluctrl <= `ALU_CTRL_ADD;
                     `FUNCT3_XORI:	aluctrl <= `ALU_CTRL_XOR;
                     `FUNCT3_ANDI: aluctrl <= `ALU_CTRL_AND;
-                    default:		aluctrl <= `ALU_CTRL_ZERO;	
+                    `FUNCT3_SL:   case(funct7)
+                                    `FUNCT7_SLLI: aluctrl <= `ALU_CTRL_SLL;
+                                    default:      aluctrl <= `ALU_CTRL_ZERO;
+                                  endcase
+                    default:		  aluctrl <= `ALU_CTRL_ZERO;	
                   endcase
       default:  aluctrl <= `ALU_CTRL_ZERO;
 	 endcase
diff --git a/xgriscv_datapath.v b/xgriscv_datapath.v
index c56deac43745946359bffff67e7618f568c65966..a2dfea20bb2ab38704ee2e1614bdb97dc6164970 100644
--- a/xgriscv_datapath.v
+++ b/xgriscv_datapath.v
@@ -59,9 +59,10 @@ module datapath(
 
 
 	//处理mux
-	mux2 #(32)   mx0(rdata2, immout, alusrcb, b);
-	mux2 #(32)   mx1(aluout, readdata, memtoreg, wdata);
-	mux3 #(32)   mx2(rdata1, 0, pc, alusrca, a);
+	mux2 #(32)   mx0(rdata2, immout, alusrcb, b); //alu input b
+	mux2 #(32)   mx1(aluout, readdata, memtoreg, wdata); // wdata input
+	mux3 #(32)   mx2(rdata1, 0, pc, alusrca, a); //alu input a
+	mux2 #(5)    mx2(rdata2, rs2, itype, shamt); //alu input shamt
 
 	imm 	im(iimm, simm, bimm, uimm, jimm, immctrl, immout);