diff --git a/xgriscv_controller.v b/xgriscv_controller.v
index be35b71e3b165f593a2923b52a4af3146f70a344..7cb96daff70712d71f28e2b26fc9d6023aeb061d 100644
--- a/xgriscv_controller.v
+++ b/xgriscv_controller.v
@@ -70,7 +70,7 @@ module controller(
   wire rv32_rd_x0 = (rd  == 5'b00000);
   wire rv32_nop		= rv32_addi & rv32_rs1_x0 & rv32_rd_x0 & (imm == 12'b0); //addi x0, x0, 0 is nop
 
-  assign itype = rv32_addri;
+  assign itype = rv32_addri | rv32_jalr;
 
   wire stype = 0;
 
@@ -78,19 +78,19 @@ module controller(
 
   wire utype = rv32_lui | rv32_auipc;
 
-  wire jtype = 0;
+  wire jtype = rv32_jal;
 
   assign immctrl = {itype, stype, btype, utype, jtype};
 
-  assign jal = 0;
+  assign jal = rv32_jal;
 
-  assign jalr = 0;
+  assign jalr = rv32_jalr;
 
   assign bunsigned = 0;
 
-  assign pcsrc = 0;
+  assign pcsrc = rv32_jal | rv32_jalr;
 
-  assign alusrca = rv32_lui ? 2'b01 : (rv32_auipc ? 2'b10 : 2'b00);
+  assign alusrca = rv32_lui ? 2'b01 : (rv32_auipc ? 2'b10 : (rv32_jal | rv32_jalr) ? 2'b11 : 2'b00);
 
   assign alusrcb = rv32_lui || rv32_auipc || rv32_addri;
 
@@ -100,7 +100,7 @@ module controller(
 
   assign memtoreg = 0;
 
-  assign regwrite = rv32_lui | rv32_auipc | rv32_addri | rv32_addrr;
+  assign regwrite = rv32_lui | rv32_auipc | rv32_addri | rv32_addrr | rv32_jal | rv32_jalr;
 
 
   always @(*)
@@ -131,7 +131,9 @@ module controller(
                     `FUNCT3_SLT:  aluctrl <= `ALU_CTRL_SLT;
                     `FUNCT3_SLTU: aluctrl <= `ALU_CTRL_SLTU;
                   endcase
-      default:  aluctrl <= `ALU_CTRL_ZERO;
+      `OP_JAL:    aluctrl <= `ALU_CTRL_ZERO;
+      `OP_JALR:   aluctrl <= `ALU_CTRL_ZERO;
+      default:    aluctrl <= `ALU_CTRL_ZERO;
 	 endcase
 
 endmodule
\ No newline at end of file
diff --git a/xgriscv_datapath.v b/xgriscv_datapath.v
index eb396e57553d5e70b49f0df0fbc2cc2461d08d6e..d5f42d1e120410125710c2e5aa9288c6d4d1dd4c 100644
--- a/xgriscv_datapath.v
+++ b/xgriscv_datapath.v
@@ -44,7 +44,7 @@ module datapath(
 	wire [11:0]				simm	= 12'b0;
 	wire [11:0]  			bimm	= 20'b0;
 	wire [19:0]				uimm	= instr[31:12];
-	wire [19:0]  			jimm	= 20'b0;
+	wire [19:0]  			jimm	= {instr[31], instr[19:12], instr[20], instr[30:21]};
 	wire [`XLEN-1:0]		immout, shftimm;
 	wire [`XLEN-1:0]		rdata1, rdata2, wdata;
 	wire [`RFIDX_WIDTH-1:0]	waddr = rd;
@@ -55,7 +55,9 @@ module datapath(
     wire                    stall = 1'b0;
 	wire [`ADDR_SIZE-1:0]   newpc;
     pcenr      	pcr(clk, reset, ~stall, newpc, pc);
-    addr_adder  pcadder(pc, `ADDR_SIZE'b100, newpc);
+    addr_adder  pcadder(pc, `ADDR_SIZE'b100, pcplus4);
+	sl1         pcsft(immout, immoutsft);
+	addr_adder  pcjal(pc, immoutsft, pcsum);
 
 	wire [4:0]              shamt;
 
@@ -65,6 +67,8 @@ module datapath(
 	mux2 #(32)   mx1(aluout, readdata, memtoreg, wdata); // wdata input
 	mux3 #(32)   mx2(rdata1, 0, pc, alusrca, a); //alu input a
 	mux2 #(5)    mx3(rdata2[4:0], instr[24:20], itype, shamt); //alu input shamt
+	mux2 #(32)   mx4(pcplus4, pcsum, pcsrc, newpc);//pc input 
+	mux2 #(32)   mx5(wdata, pcplus4, pcsrc, wdata);// wdata input pcplus4
 
 	imm 	im(iimm, simm, bimm, uimm, jimm, immctrl, immout);
 
diff --git a/xgriscv_parts.v b/xgriscv_parts.v
index a35002d843adb161c9b38ab84d9fe6f63f3a225f..c27dbd599bc6f1da5bbf70d2a4652ebc1d6b6dcc 100644
--- a/xgriscv_parts.v
+++ b/xgriscv_parts.v
@@ -132,8 +132,8 @@ module imm (
 	input	[11:0]			iimm, //instr[31:20], 12 bits
 	input	[11:0]			simm, //instr[31:25, 11:7], 12 bits
 	input	[11:0]			bimm, //instrD[31], instrD[7], instrD[30:25], instrD[11:8], 12 bits
-	input	[19:0]			uimm,
-	input	[19:0]			jimm,
+	input	[19:0]			uimm, //
+	input	[19:0]			jimm, //instr[31], instr[19:12], instr[20], instr[30:21], 20 bits
 	input	[4:0]			 immctrl,
 
 	output	reg [`XLEN-1:0] 	immout);