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Commit a16f6380 authored by 秦槿's avatar 秦槿
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alli

parent e5cb93a5
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...@@ -34,6 +34,8 @@ module alu( ...@@ -34,6 +34,8 @@ module alu(
`ALU_CTRL_XOR: aluout <= a ^ b; `ALU_CTRL_XOR: aluout <= a ^ b;
`ALU_CTRL_AND: aluout <= a & b; `ALU_CTRL_AND: aluout <= a & b;
`ALU_CTRL_SLL: aluout <= a << shamt;
//`ALU_CTRL_ZERO //`ALU_CTRL_ZERO
default: aluout <= `XLEN'b0; default: aluout <= `XLEN'b0;
endcase endcase
......
...@@ -111,7 +111,11 @@ module controller( ...@@ -111,7 +111,11 @@ module controller(
`FUNCT3_ADDI: aluctrl <= `ALU_CTRL_ADD; `FUNCT3_ADDI: aluctrl <= `ALU_CTRL_ADD;
`FUNCT3_XORI: aluctrl <= `ALU_CTRL_XOR; `FUNCT3_XORI: aluctrl <= `ALU_CTRL_XOR;
`FUNCT3_ANDI: aluctrl <= `ALU_CTRL_AND; `FUNCT3_ANDI: aluctrl <= `ALU_CTRL_AND;
default: aluctrl <= `ALU_CTRL_ZERO; `FUNCT3_SL: case(funct7)
`FUNCT7_SLLI: aluctrl <= `ALU_CTRL_SLL;
default: aluctrl <= `ALU_CTRL_ZERO;
endcase
default: aluctrl <= `ALU_CTRL_ZERO;
endcase endcase
default: aluctrl <= `ALU_CTRL_ZERO; default: aluctrl <= `ALU_CTRL_ZERO;
endcase endcase
......
...@@ -59,9 +59,10 @@ module datapath( ...@@ -59,9 +59,10 @@ module datapath(
//处理mux //处理mux
mux2 #(32) mx0(rdata2, immout, alusrcb, b); mux2 #(32) mx0(rdata2, immout, alusrcb, b); //alu input b
mux2 #(32) mx1(aluout, readdata, memtoreg, wdata); mux2 #(32) mx1(aluout, readdata, memtoreg, wdata); // wdata input
mux3 #(32) mx2(rdata1, 0, pc, alusrca, a); mux3 #(32) mx2(rdata1, 0, pc, alusrca, a); //alu input a
mux2 #(5) mx2(rdata2, rs2, itype, shamt); //alu input shamt
imm im(iimm, simm, bimm, uimm, jimm, immctrl, immout); imm im(iimm, simm, bimm, uimm, jimm, immctrl, immout);
......
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