slli

xgriscv_datapath.v

@@ -49,7 +49,7 @@ module datapath(
 	wire [`XLEN-1:0]		rdata1, rdata2, wdata;
 	wire [`RFIDX_WIDTH-1:0]	waddr = rd;
 	wire [`XLEN-1:0]        a, b;
-
+	
 
 	//更新pc
     wire                    stall = 1'b0;
@@ -57,12 +57,12 @@ module datapath(
     pcenr      	pcr(clk, reset, ~stall, newpc, pc);
     addr_adder  pcadder(pc, `ADDR_SIZE'b100, newpc);
 
-
+	wire [4:0]              shamt = instr[24:20];
 	//处理mux
 	mux2 #(32)   mx0(rdata2, immout, alusrcb, b); //alu input b
 	mux2 #(32)   mx1(aluout, readdata, memtoreg, wdata); // wdata input
 	mux3 #(32)   mx2(rdata1, 0, pc, alusrca, a); //alu input a
-	mux2 #(5)    mx3(rdata2[4:0], instr[24:20], itype, shamt); //alu input shamt
+	//mux2 #(5)    mx3(rdata2[4:0], instr[24:20], itype, shamt); //alu input shamt
 
 	imm 	im(iimm, simm, bimm, uimm, jimm, immctrl, immout);